PCI Connector Pinout - AllPinouts

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PCI = Peripheral Component Interconnect

This file is not intended to be a thorough coverage of the PCI standard. It is for informational purposes only, and is intended to give designers and hobbyists an overview of the bus so that they might be able to design their own PCI cards. Thus, I/O operations are explained in the most detail, while memory operations, which will usually not be dealt with by an I/O card, are only briefly explained. Hobbyists are also warned that, due to the higher clock speeds involved, PCI cards are more difficult to design than ISA cards or cards for other slower busses. Many companies are now making PCI prototyping cards, and, for those fortunate enough to have access to FPGA programmers, companies like Xilinx are offering PCI compliant designs which you can use as a starting point for your own projects.

PCI Universal Card 32/64 bit
  ----------------------------------------------------------------
 |    PCI         Component Side (side B)                         |
 |                                                                |
 |                                                                |
 |                                                optional        |
 |    ____     mandatory 32-bit pins            64-bit pins  _____|
 |___|    |||||||--|||||||||||||||||--|||||||--||||||||||||||
          ^     ^  ^               ^  ^     ^  ^            ^
        b01   b11  b14           b49  b52 b62  b63          b94
PCI 5V Card 32/64 bit
 |                                                optional        |
 |    ____     mandatory 32-bit pins            64-bit pins  _____|
 |___|    ||||||||||||||||||||||||||--|||||||--||||||||||||||
PCI 3.3V Card 32/64 bit
 |                                                optional        |
 |    ____     mandatory 32-bit pins            64-bit pins  _____|
 |___|    |||||||--||||||||||||||||||||||||||--||||||||||||||


Conn buspci.gif
98+22 PIN EDGE CONNECTOR at the computer.

Pin +5V +3.3V Universal Description
A1 TRST Test Logic Reset
A2 +12V +12 VDC
A3 TMS Test Mde Select
A4 TDI Test Data Input
A5 +5V +5 VDC
A6 INTA Interrupt A
A7 INTC Interrupt C
A8 +5V +5 VDC
A9 RESV01 Reserved VDC
A10 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A11 RESV03 Reserved VDC
A12 GND03 (OPEN) (OPEN) Ground or Open (Key)
A13 GND05 (OPEN) (OPEN) Ground or Open (Key)
A14 RESV05 Reserved VDC
A15 RESET Reset
A16 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A17 GNT Grant PCI use
A18 GND08 Ground
A19 RESV06 Reserved VDC
A20 AD30 Address/Data 30
A21 +3.3V01 +3.3 VDC
A22 AD28 Address/Data 28
A23 AD26 Address/Data 26
A24 GND10 Ground
A25 AD24 Address/Data 24
A26 IDSEL Initialization Device Select
A27 +3.3V03 +3.3 VDC
A28 AD22 Address/Data 22
A29 AD20 Address/Data 20
A30 GND12 Ground
A31 AD18 Address/Data 18
A32 AD16 Address/Data 16
A33 +3.3V05 +3.3 VDC
A34 FRAME Address or Data phase
A35 GND14 Ground
A36 TRDY Target Ready
A37 GND15 Ground
A38 STOP Stop Transfer Cycle
A39 +3.3V07 +3.3 VDC
A40 SDONE Snoop Done
A41 SBO Snoop Backoff
A42 GND17 Ground
A43 PAR Parity
A44 AD15 Address/Data 15
A45 +3.3V10 +3.3 VDC
A46 AD13 Address/Data 13
A47 AD11 Address/Data 11
A48 GND19 Ground
A49 AD9 Address/Data 9
A52 C/BE0 Command, Byte Enable 0
A53 +3.3V11 +3.3 VDC
A54 AD6 Address/Data 6
A55 AD4 Address/Data 4
A56 GND21 Ground
A57 AD2 Address/Data 2
A58 AD0 Address/Data 0
A59 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A60 REQ64 Request 64 bit ???
A61 VCC11 +5 VDC
A62 VCC13 +5 VDC
A63 GND Ground
A64 C/BE[7]# Command, Byte Enable 7
A65 C/BE[5]# Command, Byte Enable 5
A66 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A67 PAR64 Parity 64 ???
A68 AD62 Address/Data 62
A69 GND Ground
A70 AD60 Address/Data 60
A71 AD58 Address/Data 58
A72 GND Ground
A73 AD56 Address/Data 56
A74 AD54 Address/Data 54
A75 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A76 AD52 Address/Data 52
A77 AD50 Address/Data 50
A78 GND Ground
A79 AD48 Address/Data 48
A80 AD46 Address/Data 46
A81 GND Ground
A82 AD44 Address/Data 44
A83 AD42 Address/Data 42
A84 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
A85 AD40 Address/Data 40
A86 AD38 Address/Data 38
A87 GND Ground
A88 AD36 Address/Data 36
A89 AD34 Address/Data 34
A90 GND Ground
A91 AD32 Address/Data 32
A92 RES Reserved
A93 GND Ground
A94 RES Reserved
B1 -12V -12 VDC
B2 TCK Test Clock
B3 GND Ground
B4 TDO Test Data Output
B5 +5V +5 VDC
B6 +5V +5 VDC
B7 INTB Interrupt B
B8 INTD Interrupt D
B9 PRSNT1 Reserved
B10 RES +V I/O (+5 V or +3.3 V)
B11 PRSNT2  ??
B12 GND (OPEN) (OPEN) Ground or Open (Key)
B13 GND (OPEN) (OPEN) Ground or Open (Key)
B14 RES Reserved VDC
B15 GND Reset
B16 CLK Clock
B17 GND Ground
B18 REQ Request
B19 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
B20 AD31 Address/Data 31
B21 AD29 Address/Data 29
B22 GND Ground
B23 AD27 Address/Data 27
B24 AD25 Address/Data 25
B25 +3.3V +3.3VDC
B26 C/BE3 Command, Byte Enable 3
B27 AD23 Address/Data 23
B28 GND Ground
B29 AD21 Address/Data 21
B30 AD19 Address/Data 19
B31 +3.3V +3.3 VDC
B32 AD17 Address/Data 17
B33 C/BE2 Command, Byte Enable 2
B34 GND13 Ground
B35 IRDY Initiator Ready
B36 +3.3V06 +3.3 VDC
B37 DEVSEL Device Select
B38 GND16 Ground
B39 LOCK Lock bus
B40 PERR Parity Error
B41 +3.3V08 +3.3 VDC
B42 SERR System Error
B43 +3.3V09 +3.3 VDC
B44 C/BE1 Command, Byte Enable 1
B45 AD14 Address/Data 14
B46 GND18 Ground
B47 AD12 Address/Data 12
B48 AD10 Address/Data 10
B49 GND20 Ground
B50 (OPEN) GND (OPEN) Ground or Open (Key)
B51 (OPEN) GND (OPEN) Ground or Open (Key)
B52 AD8 Address/Data 8
B53 AD7 Address/Data 7
B54 +3.3V12 +3.3 VDC
B55 AD5 Address/Data 5
B56 AD3 Address/Data 3
B57 GND22 Ground
B58 AD1 Address/Data 1
B59 VCC08 +5 VDC
B60 ACK64 Acknowledge 64 bit ???
B61 VCC10 +5 VDC
B62 VCC12 +5 VDC
B63 RES Reserved
B64 GND Ground
B65 C/BE[6]# Command, Byte Enable 6
B66 C/BE[4]# Command, Byte Enable 4
B67 GND Ground
B68 AD63 Address/Data 63
B69 AD61 Address/Data 61
B70 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
B71 AD59 Address/Data 59
B72 AD57 Address/Data 57
B73 GND Ground
B74 AD55 Address/Data 55
B75 AD53 Address/Data 53
B76 GND Ground
B77 AD51 Address/Data 51
B78 AD49 Address/Data 49
B79 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
B80 AD47 Address/Data 47
B81 AD45 Address/Data 45
B82 GND Ground
B83 AD43 Address/Data 43
B84 AD41 Address/Data 41
B85 GND Ground
B86 AD39 Address/Data 39
B87 AD37 Address/Data 37
B88 +5V +3.3V Signal Rail +V I/O (+5 V or +3.3 V)
B89 AD35 Address/Data 35
B90 AD33 Address/Data 33
B91 GND Ground
B92 RES Reserved
B93 RES Reserved
B94 GND Ground

Notes

  • Pin 63-94 exists only on 64 bit PCI implementations.
  • +V I/O is 3.3V on 3.3V boards, 5V on 5V boards, and define signal rails on the Universal board.


Signal Descriptions:

  • AD(x): Address/Data Lines.
  • CLK: Clock. 33 MHz maximum.
  • C/BE(x): Command, Byte Enable.
  • FRAME: Used to indicate whether the cycle is an address phase or a data phase.
  • DEVSEL: Device Select.
  • IDSEL: Initialization Device Select
  • INT(x): Interrupt
  • IRDY: Initiator Ready
  • LOCK: Used to manage resource locks on the PCI bus.
  • REQ: Request. Requests a PCI transfer.
  • GNT: Grant. indicates that permission to use PCI is granted.
  • PAR: Parity. Used for AD0-31 and C/BE0-3.
  • PERR: Parity Error.
  • RST: Reset.
  • SBO: Snoop Backoff.
  • SDONE: Snoop Done.
  • SERR: System Error. Indicates an address parity error for special cycles or a system error.
  • STOP: Asserted by Target. Requests the master to stop the current transfer cycle.
  • TCK: Test Clock
  • TDI: Test Data Input
  • TDO: Test Data Output
  • TMS: Test Mode Select
  • TRDY: Target Ready
  • TRST: Test Logic Reset

The PCI bus treats all transfers as a burst operation. Each cycle begins with an address phase followed by one or more data phases. Data phases may repeat indefinitely, but are limited by a timer that defines the maximum amount of time that the PCI device may control the bus. This timer is set by the CPU as part of the configuration space. Each device has its own timer (see the Latency Timer in the configuration space).

The same lines are used for address and data. The command lines are also used for byte enable lines. This is done to reduce the overall number of pins on the PCI connector.

The Command lines (C/BE3 to C/BE0) indicate the type of bus transfer during the address phase.

C/BE Command Type
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 reserved
0101 reserved
0110 Memory Read
0111 Memory Write
1000 reserved
1001 reserved
1010 Configuration Read
1011 Configuration Write
1100 Multiple Memory Read
1101 Dual Address Cycle
1110 Memory-Read Line
1111 Memory Write and Invalidate

The three basic types of transfers are I/O, Memory, and Configuration.

PCI timing diagrams:

            ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___
        _______                                   _________
FRAME          |_________________________________|
                ______  _______  ______  ______  ______
AD      -------<______><_______><______><______><______>---
                Address  Data1    Data2   Data3   Data4
                ______  _______________________________
C/BE    -------<______><_______________________________>---
                Command   Byte Enable Signals
         ____________                                   ___
IRDY                 |_________________________________|
         _____________                                  ___
TRDY                  |________________________________|
         ______________                                 ___
DEVSEL                 |_______________________________|

PCI transfer cycle, 4 data phases, no wait states. Data is transferred on the rising edge of CLK.

                         [1]              [2]        [3]
            ___     ___     ___     ___     ___     ___     ___     ___
CLK     ___|   |___|   |___|   |___|   |___|   |___|   |___|   |___|   |__
        _______                                                  _________
FRAME          |________________________________________________|
                                   A               B               C
                ______           ______________  ______  _____________
AD      -------<______>---------<______________><______><_____________>---
                Address           Data1           Data2   Data3
                ______  ______________________________________________
C/BE    -------<______><______________________________________________>---
                Command   Byte Enable Signals
                                                         Wait
         ____________                                    _____         ___
IRDY                 |__________________________________|     |_______|
                        Wait            Wait
         ______________________         ______                         ___
TRDY                           |_______|      |_______________________|
         ______________                                                ___
DEVSEL                 |______________________________________________|

PCI transfer cycle, with wait states. Data is transferred on the rising edge of CLK at points labelled A, B, and C.

Bus Cycles:

Interrupt Acknowledge (0000)

The interrupt controller automatically recognizes and reacts to the INTA (interrupt acknowledge) command. In the data phase, it transfers the interrupt vector to the AD lines.

Special Cycle (0001)

AD15-AD0 Description
0x0000 Processor Shutdown
0x0001 Processor Halt
0x0002 x86 Specific Code
0x0003 to 0xFFFF Reserved

I/O Read (0010) and I/O Write (0011)

Input/Output device read or write operation. The AD lines contain a byte address (AD0 and AD1 must be decoded). PCI I/O ports may be 8 or 16 bits. PCI allows 32 bits of address space. On IBM compatible machines, the Intel CPU is limited to 16 bits of I/O space, which is further limited by some ISA cards that may also be installed in the machine (many ISA cards only decode the lower 10 bits of address space, and thus mirror themselves throughout the 16 bit I/O space). This limit assumes that the machine supports ISA or EISA slots in addition to PCI slots.

The PCI configuration space may also be accessed through I/O ports 0x0CF8 (Address) and 0x0CFC (Data). The address port must be written first.

Memory Read (0110) and Memory Write (0111)

A read or write to the system memory space. The AD lines contain a doubleword address. AD0 and AD1 do not need to be decoded. The Byte Enable lines (C/BE) indicate which bytes are valid.

Configuration Read (1010) and Configuration Write (1011)

A read or write to the PCI device configuration space, which is 256 bytes in length. It is accessed in doubleword units. AD0 and AD1 contain 0, AD2-7 contain the doubleword address, AD8-10 are used for selecting the addressed unit a the malfunction unit, and the remaining AD lines are not used.

Address     Bit 32      16   15           0
00          Unit ID        | Manufacturer ID
04          Status         | Command
08          Class Code               | Revision
0C          BIST  | Header | Latency | CLS
10-24            Base Address Register
28          Reserved
2C          Reserved
30          Expansion ROM Base Address
34          Reserved
38          Reserved
3C          MaxLat|MnGNT   | INT-pin | INT-line
40-FF       available for PCI unit

Multiple Memory Read (1100)

This is an extension of the memory read bus cycle. It is used to read large blocks of memory without caching, which is beneficial for long sequential memory accesses.

Dual Address Cycle (1101)

Two address cycles are necessary when a 64 bit address is used, but only a 32 bit physical address exists. The least significant portion of the address is placed on the AD lines first, followed by the most significant 32 bits. The second address cycle also contains the command for the type of transfer (I/O, Memory, etc). The PCI bus supports a 64 bit I/O address space, although this is not available on Intel based PCs due to limitations of the CPU.

Memory-Read Line (1110)

This cycle is used to read in more than two 32 bit data blocks, typically up to the end of a cache line. It is more efficient than normal memory read bursts for a long series of sequential memory accesses.

Memory Write and Invalidate (1111)

This indicates that a minimum of one cache line is to be transferred. This allows main memory to be updated, saving a cache write-back cycle.


For more information see PCI Notes


References



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